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high resolution 6 ghz fractional-n frequency synthesizer adf4157 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2007 analog devices, inc. all rights reserved. features rf bandwidth to 6 ghz 25-bit fixed modulus allows subhertz frequency resolution 2.7 v to 3.3 v power supply separate v p allows extended tuning voltage programmable charge pump currents 3-wire serial interface digital lock detect power-down mode pin compatible with the following frequency synthesizers: adf4110/adf4111/adf4112/adf4113/ adf4106/adf4153/adf4154/adf4156 cycle slip reduction for faster lock times applications satellite communications terminals, radar equipment instrumentation equipment personal mobile radio (pmr) base stations for mobile radio wireless handsets general description the adf4157 is a 6 ghz fractional-n frequency synthesizer with a 25-bit fixed modulus, allowing subhertz frequency resolution at 6 ghz. it consists of a low noise digital phase frequency detector (pfd), a precision charge pump, and a programmable reference divider. there is a - based fractional interpolator to allow programmable fractional-n division. the int and frac registers define an overall n divider, n = int + (frac/2 25 ). the adf4157 features cycle slip reduction circuitry, which leads to faster lock times without the need for modifications to the loop filter. control of all on-chip registers is via a simple 3-wire interface. the device operates with a power supply ranging from 2.7 v to 3.3 v and can be powered down when not in use. functional block diagram lock detect n counter cp rfcp3 rfcp2 rfcp4 rfcp1 reference data le 32-bit data register clk ref in av dd agnd v dd v dd dgnd r div sd out n div dgnd cpgnd dv dd v p ce r set rf in a rf in b output mux muxout ? + high z phase frequency detector adf4157 third order fractional interpolator modulus 2 25 fraction reg integer reg current setting 2 doubler 4-bit r counter charge pump csr 2 divider 05874-001 figure 1.
adf4157 rev. 0 | page 2 of 20 table of contents features .............................................................................................. 1 applications....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 specifications..................................................................................... 3 timing specifications .................................................................. 4 absolute maximum ratings............................................................ 5 thermal resistance ...................................................................... 5 esd caution.................................................................................. 5 pin configurations and function descriptions ........................... 6 typical performance characteristics ............................................. 7 circuit description........................................................................... 8 reference input section............................................................... 8 rf input stage............................................................................... 8 rf int divider............................................................................. 8 25-bit fixed modulus .................................................................. 8 int, frac, and r relationship ................................................. 8 rf r counter ................................................................................ 8 phase frequency detector (pfd) and charge pump.............. 9 muxout and lock detect..................................................... 9 input shift registers......................................................................9 program modes .............................................................................9 register maps.................................................................................. 10 frac/int register (r0) map.................................................. 11 lsb frac register (r1) map .................................................. 12 r divider register (r2) map .................................................... 13 function register (r3) map ..................................................... 15 test register (r4) map .............................................................. 16 applications information .............................................................. 17 initialization sequence .............................................................. 17 rf synthesizer: a worked example ........................................ 17 reference doubler and reference divider ............................. 17 cycle slip reduction for faster lock times........................... 17 spur mechanisms ....................................................................... 18 low frequency applications .................................................... 18 filter designadisimpll....................................................... 18 interfacing ................................................................................... 18 pcb design guidelines for the chip scale package.............. 18 outline dimensions ....................................................................... 19 ordering guide .......................................................................... 19 revision history 7/07revision 0: initial revision
adf4157 rev. 0 | page 3 of 20 specifications av dd = dv dd = 2.7 v to 3.3 v; v p = av dd to 5.5 v; agnd = dgnd = 0 v; t a = t min to t max , unless otherwise noted; dbm referred to 50 . table 1. parameter b version 1 unit test conditions/comments rf characteristics (3 v) rf input frequency (rf in ) 0.5/6.0 ghz min/max ?10 dbm/0 dbm min/max. for lowe r frequencies, ensure slew rate (sr) > 400 v/s. reference characteristics ref in input frequency 10/300 mhz min/max for f < 10 mhz, ensure slew rate > 50 v/s. ref in input sensitivity 0.4/av dd v p-p min/max for 10 mhz < ref in < 250 mhz. biased at av dd /2 2 . 0.7/av dd v p-p min/max for 250 mhz < ref in < 300 mhz. biased at av dd /2 2 . ref in input capacitance 10 pf max ref in input current 100 a max phase detector phase detector frequency 3 32 mhz max charge pump i cp sink/source programmable. high value 5 ma typ with r set = 5.1 k. low value 312.5 a typ absolute accuracy 2.5 % typ with r set = 5.1 k. r set range 2.7/10 k min/max i cp three-state leakage current 1 na typ sink and source current. matching 2 % typ 0.5 v < v cp < v p C 0.5. i cp vs. v cp 2 % typ 0.5 v < v cp < v p C 0.5. i cp vs. temperature 2 % typ v cp = v p /2. logic inputs v inh , input high voltage 1.4 v min v inl , input low voltage 0.6 v max i inh /i inl , input current 1 a max c in , input capacitance 10 pf max logic outputs v oh , output high voltage 1.4 v min open-drain 1 k pull-up to 1.8 v. v oh , output high voltage vdd C 0.4 v min cmos output chosen. v ol , output low voltage 0.4 v max i ol = 500 a. power supplies av dd 2.7/3.3 v min/v max dv dd av dd v p av dd /5.5 v min/v max i dd 29 ma max 23 ma typical. low power sleep mode 10 a typ noise characteristics phase noise figure of merit 4 ?207 dbc/hz typ adf4157 phase noise floor 5 ?137 dbc/hz typ @ 10 mhz pfd frequency. ?133 dbc/hz typ @ 25 mhz pfd frequency. phase noise performance 6 @ vco output. 5800 mhz output 7 ?87 dbc/hz typ @ 2 khz offset, 25 mhz pfd frequency. 1 operating temperature of b version is ?40c to +85c. 2 ac-coupling ensures av dd /2 bias. 3 guaranteed by design. sample tested to ensure compliance. 4 this figure can be used to calculate phase noise for any application. use the formula C207 + 10log(f pfd ) + 20logn to calculate in-band phase noise performance as seen at the vco output. 5 the synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the vco and subtracting 2 0logn (where n is the n divider value). 6 the phase noise is me asured with the eval-adf4157eb1z and the agilent e5052a phase noise system. 7 f refin = 100 mhz; f pfd = 25 mhz; offset frequency = 2 khz; rf out = 5800.25 mhz; n = 232; l oop bandwidth = 20 khz.
adf4157 rev. 0 | page 4 of 20 timing specifications av dd = dv dd = 2.7 v to 3.3 v; v p = av dd to 5.5 v; agnd = dgnd = 0 v; t a = t min to t max , unless otherwise noted; dbm referred to 50 . table 2. parameter limit at t min to t max (b version) unit test conditions/comments t 1 20 ns min le setup time t 2 10 ns min data to clock setup time t 3 10 ns min data to clock hold time t 4 25 ns min clock high duration t 5 25 ns min clock low duration t 6 10 ns min clock to le setup time t 7 20 ns min le pulse width clk data le le db23 (msb) db22 db2 (control bit c3) db1 (control bit c2) db0 (lsb) (control bit c1) t 1 t 2 t 3 t 7 t 6 t 4 t 5 05874-002 figure 2. timing diagram
adf4157 rev. 0 | page 5 of 20 absolute maximum ratings t a = 25c, gnd = agnd = dgnd = 0 v, v dd = av dd = dv dd , unless otherwise noted. thermal resistance table 3. parameter rating ja is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. v dd to gnd ?0.3 v to +4 v v dd to v dd ?0.3 v to +0.3 v table 4. thermal resistance v p to gnd ?0.3 v to +5.8 v v p to v dd ?0.3 v to +5.8 v package type ja unit digital i/o voltage to gnd ?0.3 v to v dd + 0.3 v tssop 112 c/w analog i/o voltage to gnd ?0.3 v to v dd + 0.3 v lfcsp (paddle soldered) 30.4 c/w ref in , rf in to gnd ?0.3 v to v dd + 0.3 v esd caution operating temperature range industrial (b version) ?40c to +85c storage temperature range ?65c to +125c maximum junction temperature 150c reflow soldering peak temperature 260c time at peak temperature 40 sec stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability.
adf4157 rev. 0 | page 6 of 20 pin configurations and function descriptions 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 cp cpgnd agnd av dd rf in a rf in b r set dv dd muxout le ce ref in dgnd clk data v p adf4157 top view (not to scale) 05874-003 pin 1 indicator 1 cpgnd 2 agnd 3 agnd 4 rf in b 5 rf in a 13 data 14 le 15 muxout 12 clk 11 ce 6 a v d d 7 a v d d 8 r e f i n 1 0 d g n d 9 d g n d 1 8 v p 1 9 r s e t 2 0 c p 1 7 d v d d 1 6 d v d d top view (not to scale) adf4157 05874-004 figure 3. tssop pin configuration figure 4. lfcsp pin configuration table 5. pin function descriptions tssop lfcsp mnemonic description 1 19 r set connecting a resistor between this pin and ground sets the maximum charge pump output current. the relationship between i cp and r set is set cpmax r i 5.25 = where: r set = 5.1 k. i cpmax = 5 ma. 2 20 cp charge pump output. when enabled, this provides i cp to the external loop filter which, in turn, drives the external vco. 3 1 cpgnd charge pump ground. this is th e ground return path for the charge pump. 4 2, 3 agnd analog ground. this is the ground return path of the prescaler. 5 4 rf in b complementary input to the rf prescaler. this poin t should be decoupled to the ground plane with a small bypass capacitor, typically 100 pf. 6 5 rf in a input to the rf prescaler. this small-signal input is normally ac-coupled from the vco. 7 6, 7 av dd positive power supply for the rf section. decoupling capacitors to the digital ground plane should be placed as close as possible to this pin. av dd has a value of 3 v 10%. av dd must have the same voltage as dv dd . 8 8 ref in reference input. this is a cmos in put with a nominal threshold of v dd /2 and an equivalent input resistance of 100 k. this input can be driven from a ttl or cmos crystal oscillator, or it can be ac- coupled. 9 9, 10 dgnd digital ground. 10 11 ce chip enable. a logic low on this pin powers down the device and puts the charge pump output into three- state mode. 11 12 clk serial clock input. this serial clock is used to clock in the serial data to the registers. the data is latched into the shift register on the clk rising edge . this input is a high impedance cmos input. 12 13 data serial data input. the serial data is loaded msb first with the three lsbs being the control bits. this input is a high impedance cmos input. 13 14 le load enable, cmos input. when le is high, the data st ored in the shift registers is loaded into one of the five latches, the latch being selected using the control bits. 14 15 muxout this multiplexer output allows the lock detect, the sc aled rf, or the scaled reference frequency to be accessed externally. 15 16, 17 dv dd positive power supply for the digital section. decoupling capacitors to the digital ground plane should be placed as close as possible to this pin. dv dd has a value of 3 v 10%. dv dd must have the same voltage as av dd . 16 18 v p charge pump power supply. this should be greater than or equal to v dd . in systems where v dd is 3 v, it can be set to 5.5 v and used to drive a vco with a tuning range of up to 5.5 v.
adf4157 rev. 0 | page 7 of 20 typical performance characteristics pfd = 25 mhz, loop bandwidth = 20 khz, reference = 100 mhz, i cp = 313 a, phase noise measurements taken on the agilent e5052a phase noise system. 10 ?40 09 frequency (ghz) power (dbm) 5 0 ?5 ?10 ?15 ?20 ?25 ?30 ?35 12345678 p = 4/5 p = 8/9 05874-016 6.00 5.65 ?100 900 time (s) frequency (ghz) 5.95 5.90 5.85 5.80 5.75 5.70 0 100 200 300 400 500 600 700 800 csr off csr on 05874-019 figure 5. rf input sensitivity figure 8. lock time for 200 mhz jump from 5705 mhz to 5905 mhz with csr on and off 0 ?40 05 0 0 5.65 5.60 5.95 5.90 5.85 5.80 5.75 5.70 ?100 900 time (s) frequency (ghz) frequency (mhz) power (dbm) 100 200 300 400 v dd = 3v ?5 ?10 ?15 ?20 ?25 ?30 ?35 csr on 05874-017 0 100 200 300 400 500 600 700 800 csr off 05874-020 . 0 figure 9. lock time for 200 mhz jump from 5905 mhz to 5705 mhz with csr on and off figure 6. reference input sensitivity 0 ?160 1k 10m frequency (hz) phase noise (dbc/hz) ?20 ?40 ?60 ?80 ?100 ?120 ?140 10k 100k 1m rf = 5800.25mhz, pfd = 25mhz, n = 232, frac = 335544, frequency resolution = 0.74hz, 20khz loop bw, i cp = 313a, dsb integrated phase error = 0.97 rms, phase noise @ 2khz = ?87dbc/hz. 05874-018 6 ?6 05 05874-021 v cp (v) i cp (ma) 4 2 0 ?2 ?4 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 figure 10. charge pump output characteristics, pump up and pump down figure 7. phase noise and spurs (note that the 250 khz spur is an integer boundary spur; see the spur mechanisms section for more information.)
adf4157 rev. 0 | page 8 of 20 circuit description int, frac, and r relationship reference input section the int and frac values, in conjunction with the r counter, make it possible to generate output frequencies that are spaced by fractions of the phase frequency detector (pfd). see the the reference input stage is shown in figure 11 . sw1 and sw2 are normally closed switches. sw3 is normally open. when power-down is initiated, sw3 is closed and sw1 and sw2 are opened. this ensures that there is no loading of the ref in pin on power-down. rf synthesizer: a worked example section for more information. the rf vco frequency ( rf out ) equation is rf out = f pfd (int + ( frac/ 2 25 )) (1) buffer to r counter ref in 100k ? nc sw2 sw3 nc nc sw1 power-down control 05874-005 where: rf out is the output frequency of the external voltage controlled oscillator (vco). int is the preset divide ratio of the binary 12-bit counter (23 to 4095). frac is the numerator of the fractional division (0 to 2 25 ? 1). figure 11 reference input stage f pfd = ref in [(1 + d )/( r ( 1 +t))] (2) rf input stage where: ref in is the reference input frequency. d is the ref in doubler bit. r is the preset divide ratio of the binary 5-bit programmable reference counter (1 to 32). t is the ref in divide-by-2 bit (0 or 1). the rf input stage is shown in figure 12 . it is followed by a 2-stage limiting amplifier to generate the current-mode logic (cml) clock levels needed for the prescaler. bias generator 1.6v agnd av dd 2k? 2k ? rf in b rf in a 0 5874-006 rf r counter the 5-bit rf r counter allows the input reference frequency (ref in ) to be divided down to produce the reference clock to the pfd. division ratios from 1 to 32 are allowed. third-order fractional interpolator frac value mod reg int reg rf n divider n = int + frac/mod from rf input stage to pfd n-counter 05874-007 figure 12 rf input stage rf int divider figure 13 rf n divider the rf int counter allows a divi sion ratio in the pll feedback counter. division ratios from 23 to 4095 are allowed. 25-bit fixed modulus the adf4157 has a 25-bit fixed modulus. this allows output frequencies to be spaced with a resolution of f res = f pfd /2 25 where f pfd is the frequency of the phase frequency detector (pfd). for example, with a pfd frequency of 10 mhz, frequency steps of 0.298 hz are possible.
adf4157 rev. 0 | page 9 of 20 phase frequency detector (pfd) and charge pump input shift registers the adf4157 digital section includes a 5-bit rf r counter, a 12-bit rf n counter, and a 25-bit frac counter. data is clocked into the 32-bit shift register on each rising edge of clk. the data is clocked in msb first. data is transferred from the shift register to one of five latches on the rising edge of le. the destination latch is determined by the state of the three control bits (c3, c2, and c1) in the shift register. these are the three lsbs, db2, db1, and db0, as shown in the pfd takes inputs from the r counter and the n counter and produces an output proportional to the phase and frequency difference between them. figure 14 is a simplified schematic of the phase frequency detector. the pfd includes a fixed delay element that sets the width of the antibacklash pulse, which is typically 3 ns. this pulse ensures that there is no dead zone in the pfd transfer function and gives a consistent reference spur level. figure 2 . the truth table for these bits is shown in table 6 . figure 16 shows a summary of how the latches are programmed. u3 clr2 q2 d2 u2 down up hi hi cp ?in +in charge pump delay clr1 q1 d1 u1 05874-008 program modes table 6 and figure 16 through figure 21 show how to set up the program modes in the adf4157. several settings in the adf4157 are double-buffered. these include the lsb frac value, r counter value, reference doubler, and current setting. this means that two events have to occur before the part uses a new value of any of the double-buffered settings. first, the new value is latched into the device by writing to the appropriate register. second, a new write must be performed on register r0. figure 14. pfd simplified schematic for example, updating the fractional value can involve a write to the 13 lsb bits in r1 and the 12 msb bits in r0. r1 should be written to first, followed by the write to r0. the frequency change begins after the write to r0. double buffering ensures that the bits written to in r1 do not take effect until after the write to r0. muxout and lock detect the output multiplexer on the adf4157 allows the user to access various internal points on the chip. the state of muxout is controlled by m4, m3, m2, and m1 (see figure 17 ). figure 15 shows the muxout section in block diagram form. table 6. c3, c2, and c1 truth table control bits 05874-009 a nalog lock detect muxout dv dd three-state output n divider output dv dd dgnd dgnd r divider output digital lock detect serial data output clk divider output r divider/2 n divider/2 control mux c3 c2 c1 register 0 0 0 register r0 0 0 1 register r1 0 1 0 register r2 0 1 1 register r3 1 0 0 register r4 figure 15. muxout schematic
adf4157 rev. 0 | page 10 of 20 register maps db31 control bits 12-bit msb fractional value (frac) 12-bit integer value (int) muxout control db30 db29 db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 0 m4 m3 m2 m1 n12 n11 n10 n9 n8 n7 n6 n5 n4 n3 n2 n1 f25 f24 f23 f22 f21 f20 f19 f18 f17 f16 f15 f14 c3(0) c2(0) c1(0) reserved frac/int register (r0) db31 control bits reserved 13-bit lsb fractional value (frac) (dbb) reserved db30 db29 db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 f13 f12 f11 f10 f9 f8 f7 f6 f5 f4 f3 f2 f1 0 0 0 0 0 0 0 0 0 0 0 0 c3(0) c2(0) c1(1) lsb frac register (r1) db31 reserved pd pd polarity ldp counter reset cp three-state control bits db30 db29 db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 00000000000000000u12000000u11u10u9u8u7c3(0)c2(1)c1(1) function register (r3) db31 reserved control bits db30 db29 db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 00000000000000000000000000000c3(1)c2(0)c1(0) test register (r4) notes 1. dbb = double buffered bit(s). db31 reserved 5-bit r-counter reserved reserved csr en reserved prescaler rdiv2 dbb current setting reference doubler dbb control bits db30 db29 db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 000c1cpi4cpi3cpi2cpi10p1u2u1r5r4r3r2r1000000000000c3(0)c2(1)c1(0) r divider register (r2) dbb dbb 05874-010 sd reset reserved figure 16. register summary
adf4157 rev. 0 | page 11 of 20 frac/int register (r0) map with r0[2, 1, 0] set to [0, 0, 0], the on-chip frac/int register is programmed as shown in figure 17 . reserved bit the reserved bit should be set to 0 for normal operation. muxout the on-chip multiplexer is controlled by db[30], db[29], db[28] and db[27] on the adf4157. see figure 17 for the truth table. 12-bit int value these twelve bits control what is loaded as the int value. this is used to determine the overall feedback division factor. it is used in equation 1. see the int, frac, and r relationship section for more information. 12-bit msb frac value these twelve bits, along with bits db[27:15] in the lsb frac register (r1), control what is loaded as the frac value into the fractional interpolator. this is part of what determines the overall feedback division factor. it is also used in equation 1. these 12 bits are the most significant bits (msb) of the 25-bit frac value, and bits db[27:15] in the lsb frac register (r1) are the least significant bits (lsb). see the rf synthesizer: a worke d e x ampl e section for more information. db31 control bits 12-bit msb fractional value (frac) 12-bit integer value (int) muxout control db30 db29 db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 0 m4 m3 m2 m1 n12 n11 n10 n9 n8 n7 n6 n5 n4 n3 n2 n1 f25 f24 f23 f22 f21 f20 f19 f18 f17 f16 f15 f14 c3(0) c2(0) c1(0) reserved m4 m3 m2 m1 output 0 0 0 0 three-state output 0001dv dd 0010dgnd 0 0 1 1 r divider output 0 1 0 0 n divider output 0 1 0 1 reserved 0 1 1 0 digital lock detect 0 1 1 1 serial data output 1 0 0 0 reserved 1 0 0 1 reserved 1010clkdivider 1 0 1 1 reserved 1 1 0 0 reserved 1 1 0 1 r divider/2 1 1 1 0 n divider/2 1 1 1 1 reserved f12 f11 .......... f2 f1 msb fractional value (frac)* 0 0 .......... 0 0 0 0 0 .......... 0 1 1 0 0 .......... 1 0 2 0 0 .......... 1 1 3 . . .......... . . . . . .......... . . . . . .......... . . . 1 1 .......... 0 0 4092 1 1 .......... 0 1 4093 1 1 .......... 1 0 4094 1 1 .......... 1 1 4095 n12n11n10n9n8n7n6n5n4n3n2n1 integer value (int) 0 0 0 00001011123 0 0 0 00001100024 0 0 0 00001100125 0 0 0 00001101026 . . . .......... . . . .......... . . . .......... 1 1 1 1111111014093 1 1 1 1111111104094 1 1 1 1111111114095 *the frac value is made up of the 12-bit msb stored in register 0, and the 13-bit lsb register stored in register 1. frac value = 13-bit lsb + 12-bit msb 2 13 . 05874-011 figure 17. frac/int register (r0) map
adf4157 rev. 0 | page 12 of 20 lsb frac register (r1) map with r1[2, 1, 0] set to [0, 0, 1], the on-chip lsb frac register is programmed as shown in figure 18 . 13-bit lsb frac value these thirteen bits, along with bits db[14:3] in the int/frac register (r0), control what is loaded as the frac value into the fractional interpolator. this is part of what determines the overall feedback division factor. it is also used in equation 1. these 13 bits are the least significant bits of the 25-bit frac value, and bits db[14:3] in the int/frac register are the most significant bits. see the rf synthesizer: a worked example section for more information. reserved bits all reserved bits should be set to 0 for normal operation. db31 control bits reserved 13-bit lsb fractional value (frac) reserved db30 db29 db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 f13 f12 f11 f10 f9 f8 f7 f6 f5 f4 f3 f2 f1 0 0 0 0 0 0 0 0 0 0 0 0 c3(0) c2(0) c1(1) f25 f24 .......... f14 f13 lsb fractional value (frac)* 0 0 .......... 0 0 0 0 0 .......... 0 1 1 0 0 .......... 1 0 2 0 0 .......... 1 1 3 . . .......... . . . . . .......... . . . . . .......... . . . 1 1 .......... 0 0 8188 1 1 .......... 0 1 8189 1 1 .......... 1 0 8190 1 1 .......... 1 1 8191 *the frac value is made up of the 12-bit msb stored in register 0, and the 13-bit lsb register stored in register 1. frac value = 13-bit lsb + 12-bit msb 2 13 . 05874-012 figure 18. lsb frac register (r1) map
adf4157 rev. 0 | page 13 of 20 r divider register (r2) map with r1[2, 1, 0] set to [0, 1, 0], the on-chip r divider register is programmed as shown in figure 19 . csr enable setting this bit to 1 enables cycle slip reduction. this is a method for improving lock times. note that the signal at the pfd must have a 50% duty cycle in order for cycle slip reduction to work. in addition, the charge pump current setting must be set to a minimum. see the cycle slip reduction for faster lock times section for more information. note also that the cycle slip reduction feature can only be operated when the phase detector polarity setting is positive (db6 in register r3). it cannot be used if the phase detector polarity is set to negative. charge pump current setting db[27], db[26], db[25], and db[24] set the charge pump current setting. this should be set to the charge pump current that the loop filter is designed with (see figure 19 ). prescaler (p/p + 1) the dual-modulus prescaler (p/p + 1), along with the int, frac, and mod counters, determines the overall division ratio from the rf in to the pfd input. operating at cml levels, it takes the clock from the rf input stage and divides it down for the counters. it is based on a synchronous 4/5 core. when set to 4/5, the maximum rf frequency allowed is 3 ghz. therefore, when operating the adf4157 above 3 ghz, the prescaler must be set to 8/9. the prescaler limits the int value. with p = 4/5, n min = 23. with p = 8/9, n min = 75. rdiv2 setting this bit to 1 inserts a divide-by-2 toggle flip flop between the r counter and the pfd. this can be used to provide a 50% duty cycle signal at the pfd for use with cycle slip reduction. reference doubler setting db[20] to 0 feeds the ref in signal directly to the 5-bit rf r counter, disabling the doubler. setting this bit to 1 multiplies the ref in frequency by a factor of 2 before feeding into the 5-bit r counter. when the doubler is disabled, the ref in falling edge is the active edge at the pfd input to the fractional synthesizer. when the doubler is enabled, both the rising edge and falling edge of ref in become active edges at the pfd input. the maximum allowed ref in frequency when the doubler is enabled is 30 mhz. 5-bit r counter the 5-bit r counter allows the input reference frequency (ref in ) to be divided down to produce the reference clock to the phase frequency detector (pfd). division ratios from 1 to 32 are allowed. reserved bits all reserved bits should be set to 0 for normal operation.
adf4157 rev. 0 | page 14 of 20 db31 reserved 5-bit r-counter reserved reserved csr en reserved prescaler rdiv2 current setting reference doubler control bits db30 db29 db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 000c1cpi4cpi3cpi2cpi10p1u2u1r5r4r3r2r1000000000000c3(0)c2(1)c1(0 ) c1 cycle slip reduction 0disabled 1enabled u1 reference doubler 0 disabled 1enabled r5 r4 r3 r2 r1 r counter divide ratio 000011 000102 000113 001004 ..... ..... ..... 1110129 1111 .30 1111131 0000032 u2 r divider 0disabled 1enabled p1 prescaler 04/5 18/9 i cp (ma) cpi4 cpi3 cpi2 cpi1 5.1k ? 00000.31 00010.63 00100.94 00111.25 01001.57 01011.88 01102.19 01112.5 10002.81 10013.13 10103.44 10113.75 11004.06 11014.38 11104.69 11115 05874-013 figure 19. r divider register (r2) map
adf4157 rev. 0 | page 15 of 20 function register (r3) map with r2[2, 1, 0] set to [0, 1, 1], the on-chip function register is programmed as shown in figure 20 . reserved bits all reserved bits should be set to 0 for normal operation. - reset for most applications, db14 should be set to 0. when db14 is set to 0, the - modulator is reset on each write to register 0. if it is not required that the - modulator be reset on each register 0 write, this bit should be set to 1. lock detect precision (ldp) when db[7] is programmed to 0, 24 consecutive pfd cycles of 15 ns must occur before digital lock detect is set. when this bit is programmed to 1, 40 consecutive reference cycles of 15 ns must occur before digital lock detect is set. phase detector polarity db[6] in the adf4157 sets the phase detector polarity. when the vco characteristics are positive, this should be set to 1. when they are negative, it should be set to 0. rf power-down db[5] on the adf4157 provides the programmable power- down mode. setting this bit to 1 performs a power-down. setting this bit to 0 returns the synthesizer to normal operation. while in software power-down mode, the part retains all information in its registers. only when supplies are removed are the register contents lost. when a power-down is activated, the following events occur: 1. all active dc current paths are removed. 2. the synthesizer counters are forced to their load state conditions. 3. the charge pump is forced into three-state mode. 4. the digital lock detect circuitry is reset. 5. the rf in input is debiased. 6. the input register remains active and capable of loading and latching data. rf charge pump three-state db[4] puts the charge pump into three-state mode when programmed to 1. it should be set to 0 for normal operation. rf counter reset db[3] is the rf counter reset bit for the adf4157. when this is 1, the rf synthesizer counters are held in reset. for normal operation, this bit should be 0. db31 reserved pd pd polarity ldp counter reset cp three-state control bits db30 db29 db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 00000000000000000u12000000u11u10u9u8u7c3(0)c2(1)c1(1) u9 power down 0 disabled 1enabled u11 ldp 0 24 pfd cycles 1 40 pfd cycles u7 counter reset 0disabled 1enabled u10 pd polarity 0negative 1positive u8 cp three-state 0disabled 1enabled 05874-014 sd reset reserved u12 sd reset 0 enabled 1 disabled fiure 20. function reister r3 ap
adf4157 rev. 0 | page 16 of 20 test register (r4) map reserved bits with r3[2, 1, 0] set to [1, 0, 0], the on-chip test register (r4) is programmed as shown in figure 21 . db[31:3] should be set to 0 in this register. db31 reserved control bits db30 db29 db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 00000000000000000000000000000c3(1)c2(0)c1(0 ) set these bits to 0 05874-015 figure 21. test register (r4) map
adf4157 rev. 0 | page 17 of 20 applications information initialization sequence after powering up the part, this programming sequence must be followed: 1. test register (r4) 2. function register (r3) 3. r divider register (r2) 4. lsb frac register (r1) 5. frac/int register (r0) rf synthesizer: a worked example the following equation governs how the synthesizer should be programmed: rf out = [ n + (frac/ 2 25 )] [ f pfd ] (3) where: rf out is the rf frequency output. n is the integer division factor. frac is the fractionality. f pfd = ref in [(1 + d )/( r ( 1 + t))] (4) where: ref in is the reference frequency input. d is the rf ref in doubler bit. r is the rf reference division factor. t is the reference divide-by-2 bit (0 or 1). for example, in a system where a 5.8002 ghz rf frequency output (rf out ) is required and a 10 mhz reference frequency input (ref in ) is available, the frequency resolution is f res = ref in /2 25 f res = 10 mhz/2 25 = 0.298 hz from equation 4, f pfd = [10 mhz (1 + 0)/1] = 10 mhz 5.8002 ghz = 10 mhz ( n + frac/ 2 25 ) calculating n and frac values, n = int ( rf out / f pfd ) = 580 frac = f msb 2 13 + f lsb f msb = int (((rf out / f pfd ) ? n) 2 12 ) = 81 f lsb = int (((((rf out / f pfd ) ? n) 2 12 ) ? f msb ) 2 13 ) = 7537 where: f msb is the 12-bit msb frac value in register r0. f lsb is the 13-bit lsb frac value in register r1. int () makes an integer of the argument in brackets. reference doubler an d reference divider the reference doubler on-chip allows the input reference signal to be doubled. this is useful for increasing the pfd comparison frequency. making the pfd frequency higher improves the noise performance of the system. doubling the pfd frequency usually improves noise performance by 3 db. it is important to note that the pfd cannot be operated above 32 mhz due to a limitation in the speed of the - circuit of the n divider. cycle slip reduction for faster lock times in fast-locking applications, a wide loop filter bandwidth is required for fast frequency acquisition, resulting in increased integrated phase noise and reduced spur attenuation. using cycle slip reduction, the loop bandwidth can be kept narrow to reduce integrated phase noise and attenuate spurs while still realizing fast lock times. cycle slips cycle slips occur in integer-n/fractional-n synthesizers when the loop bandwidth is narrow compared to the pfd frequency. the phase error at the pfd inputs accumulates too fast for the pll to correct, and the charge pump temporarily pumps in the wrong direction, slowing down the lock time dramatically. the adf4157 contains a cycle slip reduction circuit to extend the linear range of the pfd, allowing faster lock times without loop filter changes. when the adf4157 detects that a cycle slip is about to occur, it turns on an extra charge pump current cell. this outputs a constant current to the loop filter or removes a constant current from the loop filter (depending on whether the vco tuning voltage needs to increase or decrease to acquire the new frequency). the effect is that the linear range of the pfd is increased. stability is main- tained because the current is constant and is not a pulsed current. if the phase error increases again to a point where another cycle slip is likely, the adf4157 turns on another charge pump cell. this continues until the adf4157 detects that the vco frequency has gone past the desired frequency. it then begins to turn off the extra charge pump cells one by one until they are all turned off and the frequency is settled. up to seven extra charge pump cells can be turned on. in most applications, it is enough to eliminate cycle slips altogether, giving much faster lock times. setting bit db28 in the r divider register (r2) to 1 enables cycle slip reduction. note that a 45% to 55% duty cycle is needed on the signal at the pfd in order for csr to operate correctly. the reference divide-by-2 flip-flop can help to provide a 50% duty cycle at the pfd. for example, if a 100 mhz reference frequency is available, and the user wants to run the pfd at 10 mhz, setting the r divide factor to 10 results in a 10 mhz pfd signal that is not 50% duty cycle. by setting the r divide factor to 5 and enabling the reference divide-by-2 bit, a 50% duty cycle 10 mhz signal can be achieved. note that the cycle slip reduction feature can only be operated when the phase detector polarity setting is positive (db6 in register r3). it cannot be used if the phase detector polarity is set to negative.
adf4157 rev. 0 | page 18 of 20 spur mechanisms the fractional interpolator in the adf4157 is a third-order - modulator (sdm) with a 25-bit fixed modulus (mod). the sdm is clocked at the pfd reference rate (f pfd ) that allows pll output frequencies to be synthesized at a channel step resolution of f pfd /mod. the various spur mechanisms possible with fractional-n synthesizers, and how they affect the adf4157, are discussed in this section. fractional spurs in most fractional synthesizers, fractional spurs can appear at the set channel spacing of the synthesizer. in the adf4157, these spurs do not appear. the high value of the fixed modulus in the adf4157 makes the - modulator quantization error spectrum look like broadband noise, effectively spreading the fractional spurs into noise. integer boundary spurs interactions between the rf vco frequency and the pfd frequency can lead to spurs known as integer boundary spurs. when these frequencies are not integer related (which is the purpose of the fractional-n synthesizer), spur sidebands appear on the vco output spectrum at an offset frequency that corresponds to the beat note or difference frequency between an integer multiple of the pfd and the vco frequency. these spurs are named integer boundary spurs because they are more noticeable on channels close to integer multiples of the pfd where the difference frequency can be inside the loop band- width. these spurs are attenuated by the loop filter. figure 7 shows an integer boundary spur. the rf frequency is 5800.25 mhz, and the pfd frequency is 25 mhz. the integer boundary spur is 250 khz from the carrier at an integer times the pfd frequency (232 25 mhz = 5800 mhz). the spur also appears on the upper sideband. reference spurs reference spurs are generally not a problem in fractional-n synthesizers because the reference offset is far outside the loop bandwidth. however, any reference feedthrough mechanism that bypasses the loop can cause a problem. one such mechanism is the feedthrough of low levels of on-chip reference switching noise out through the rf in pin back to the vco, resulting in reference spur levels as high as C90 dbc. care should be taken in the pcb layout to ensure that the vco is well separated from the input reference to avoid a possible feedthrough path on the board. low frequency applications the specification on the rf input is 0.5 ghz minimum; however, rf frequencies lower than this can be used providing the minimum slew rate specification of 400 v/s is met. an appropriate lvds driver can be used to square up the rf signal before it is fed back to the adf4157 rf input. the fin1001 from fairchild semiconductor is one such lvds driver. filter designadisimpll a filter design and analysis program is available to help the user implement pll design. visit www.analog.com/pll for a free download of the adisimpll? software. the software designs, simulates, and analyzes the entire pll frequency domain and time domain response. various passive and active filter architectures are allowed. interfacing the adf4157 has a simple spi-compatible serial interface for writing to the device. clk, data, and le control the data transfer. when latch enable (le) is high, the 29 bits that have been clocked into the input register on each rising edge of sclk are transferred to the appropriate latch. see figure 2 for the timing diagram and table 6 for the latch truth table. the maximum allowable serial clock rate is 20 mhz. pcb design guidelines for the chip scale package the lands on the chip scale package (cp-20) are rectangular. the printed circuit board pad for these should be 0.1 mm longer than the package land length and 0.05 mm wider than the package land width. the land should be centered on the pad. this ensures that the solder joint size is maximized. the bottom of the chip scale package has a central thermal pad. the thermal pad on the printed circuit board should be at least as large as this exposed pad. on the printed circuit board, there should be a clearance of at least 0.25 mm between the thermal pad and the inner edges of the pad pattern. this ensures that shorting is avoided. thermal vias can be used on the printed circuit board thermal pad to improve thermal performance of the package. if vias are used, they should be incorporated into the thermal pad at 1.2 mm pitch grid. the via diameter should be between 0.3 mm and 0.33 mm, and the via barrel should be plated with 1 ounce of copper to plug the via. the user should connect the printed circuit board thermal pad to agnd.
adf4157 rev. 0 | page 19 of 20 outline dimensions 16 9 8 1 pin 1 seating plane 8 0 4.50 4.40 4.30 6.40 bsc 5.10 5.00 4.90 0.65 bsc 0.15 0.05 1.20 max 0.20 0.09 0.75 0.60 0.45 0.30 0.19 coplanarity 0.10 compliant to jedec standards mo-153-ab figure 22. 16-lead thin shrink small outline package [tssop] (ru-16) dimensions shown in millimeters 1 20 5 6 11 16 15 10 2.25 2.10 sq 1.95 0.75 0.55 0.35 0.30 0.23 0.18 0.50 bsc 12 max 0.20 ref 0.80 max 0.65 typ 0.05 max 0.02 nom 1.00 0.85 0.80 seating plane pin 1 indicato r top view 3.75 bcs sq 4.00 bsc sq coplanarity 0.08 0.60 max 0.60 max 0.25 min compliant to jedec standards mo-220-vggd-1 pin 1 indicator figure 23. 20-lead lead frame chip scale package [lfcsp_vq] 4mm 4 mm body, very thin quad (cp-20-1) dimensions shown in millimeters ordering guide model description temperature range package option adf4157bruz 16-lead thin shrink small outline package [tssop] ?40c to +85c ru-16 1 adf4157bruz-rl 16-lead thin shrink small outline package [tssop] ?40c to +85c ru-16 1 adf4157bruz-rl7 16-lead thin shrink small outline package [tssop] ?40c to +85c ru-16 1 adf4157bcpz 20-lead lead frame chip scale package [lfcsp_vq] ?40c to +85c cp-20-1 1 adf4157bcpz-rl 20-lead lead frame chip scale package [lfcsp_vq] ?40c to +85c cp-20-1 1 adf4157bcpz-rl7 20-lead lead frame chip scale package [lfcsp_vq] ?40c to +85c cp-20-1 1 eval-adf4157eb1z evaluation board 1 1 z = rohs compliant part.
adf4157 rev. 0 | page 20 of 20 notes ? 2007 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d05874-0-7/07(0)

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